Conventional approaches to providing a high voltage switch in an EEPROM or a FLASH memory can include the implementation of the switch with a triple-well process. In a triple-well process, both P-channel and N-channel transistors may be implemented with controllable substrates and may therefore operate more efficiently in the high voltage domain. The implementation of the N-channel transistors in this way may allow for switching of the negative voltages associated with the programming of the device. U.S. Pat. No. 5,701,272 illustrates one such approach. However, a triple-well process is more expensive to fabricate than a twin-well process due to the additional fabrication steps required. As a result, certain devices are implemented in a twin-well process in order to satisfy design constraints other than those that may be associated with the implementation of on-chip charge pumping and switching circuitry.
When implementing a switch circuit using a twin-well process and conventional approaches such as, by way of example, in an N-well process with a P-substrate, it is difficult to switch the high negative voltages associated with the programming of selected memory cells without the use of N-channel transistors. N-channel transistors cannot be used here for negative switching since the source/drain diffusion diode junctions would forward bias to the grounded P-substrate. P-channel transistors used for controlling negative voltages are difficult to turn on since the gates of these P-channel transistors would have to go even further negative making the gate drivers, in turn, even harder to control.
Certain approaches to implementing a switch in a twin-well process have the disadvantages of not fully passing the negative voltages. For example, a -12V may be reduced to a -6V, which decreases the overall efficiency of the circuit as well as increasing the amount of negative voltage that an on-chip charge pump must generate. Specifically, if a -12V is desired for programming the memory, the pump may have to generate a -15V, which may be at the limit of certain process technologies.
Charge pumps may be implemented to generate a very high voltage (e.g., 15V) or a very low voltage (e.g., -15V). The output of the charge pump or pumps must then be directed to the selected memory cells for the various erasing/programming or verifying/reading functions.